The present application relates to semiconductor technology, and more particularly to a semiconductor structure containing a first fin structure containing a silicon germanium alloy fin portion having a germanium content and a first strain, and a second fin structure containing a silicon germanium alloy fin portion having the same germanium content as the first silicon germanium alloy fin portion and a second strain, wherein the second strain is different from the first strain. The present application also provides a method of forming such a semiconductor structure from a substrate that contains silicon germanium alloy regions having different germanium content.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, silicon fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Silicon fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to extend these devices for multiple technology nodes such as, for example, 10 nm and beyond, there is a need to boost the performance with high-mobility channels. In such FinFET devices, a fin containing a silicon germanium alloy is one promising channel material because of its high-carrier mobility.
Device scaling and the necessary fin thickness scaling to maintain electrostatic integrity continues to reduce the gate contact area making a replacement metal gate process challenging. Current and future technologies nodes limit the gate length to less than 20 nm resulting in very tight process tolerances for workfunction tuning layers in the replacement metal gate process. This problem is further exacerbated for Fin geometries where thin metal layers have to be deposited conformally on the Fin sidewalls.
In view of the above, there is a need for providing a semiconductor structure containing multiple threshold voltage adjusted silicon germanium alloy fins which avoids the drawbacks mentioned above for prior art processes.